1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor and, more particularly, to a technology effectively applied to a conductive pattern formed by an electroconductive material in a groove formed in an insulating film.
2. Description of Related Art
With the recent trend toward higher integration and further microminiaturization, there has been demand for multilayer wiring structures and micro-wiring or the like. In addition, there has been growing need for lower resistance of a conductive pattern material in response to the demand for lower power consumption and higher speed in semiconductor devices.
To meet such needs, heretofor, a groove pattern is formed in an interlayer insulating film formed on the surface of a substrate, and an electroconductive material, such as copper (Cu), is embedded. Thereafter, unwanted electroconductive material at the top of the groove is removed by the chemical mechanical polishing (CMP) process thereby to complete the wiring. This technology is known as “damascene process”.
A conventional semiconductor device having a multilayer wiring structure has been implemented, in which a upper interconnection and a third conductive pattern that are formed by the damascene process are deposited on a lower interconnection formed also by the damascene process.
The demand for higher integration in semiconductor devices in recent years, however, has been accelerating, leading to the increasing demand for enhanced multilayer wiring and further reduced wiring width.
In serving the aforesaid need, the conventional semiconductor devices have been incurring an increased capacitance between conductive patterns attributable to reduced wiring pitches, and slower operating speed of semiconductor elements due to the increased capacitance between conductive patterns, thus posing a serious problem. In other words, it is becoming difficult for the aforesaid semiconductor device having the conventional multilayer wiring structure to fully realize required higher speed.
Hence, in recent years, an attempt has been made to use an insulating film with a lower dielectric constant (relative dielectric constant ∈=below 2.5) for the interlayer insulating film between conductive patterns in a semiconductor device employing the Damascene process. Such an insulating film may be, for example, an insulating film with low dielectric constant to which an organic material or the like has been added.
However, using such an insulating film with low dielectric constant as the interlayer insulating film has been posing a new problem, although it is able to provide lower relative dielectric constant. More specifically, the insulating film with low dielectric constant is much coarser than a conventionally used silicon oxide film, so that it cannot provide satisfactory mechanical strength and thermal conductivity required of an interlayer insulating film for a semiconductor device having the multilayer wiring structure.